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axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../../AMDDesignTools/2025.2/Vivado/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"incdir="C:/AMDDesignTools/2025.2/Vivado/data/rsb/busdef"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"
xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../AMDDesignTools/2025.2/Vivado/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"incdir="C:/AMDDesignTools/2025.2/Vivado/data/rsb/busdef"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"
axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../AMDDesignTools/2025.2/Vivado/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"incdir="C:/AMDDesignTools/2025.2/Vivado/data/rsb/busdef"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"
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axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../AMDDesignTools/2025.2/Vivado/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"incdir="C:/AMDDesignTools/2025.2/Vivado/data/rsb/busdef"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"
axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../AMDDesignTools/2025.2/Vivado/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"incdir="C:/AMDDesignTools/2025.2/Vivado/data/rsb/busdef"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"
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rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../AMDDesignTools/2025.2/Vivado/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"incdir="C:/AMDDesignTools/2025.2/Vivado/data/rsb/busdef"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"
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xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../../AMDDesignTools/2025.2/Vivado/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"incdir="C:/AMDDesignTools/2025.2/Vivado/data/rsb/busdef"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"
xpm_memory.sv,systemverilog,xpm,../../../../../../../../../../AMDDesignTools/2025.2/Vivado/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"incdir="C:/AMDDesignTools/2025.2/Vivado/data/rsb/busdef"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"
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axi_gpio_v2_0_vh_rfs.vhd,vhdl,axi_gpio_v2_0_37,../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/0271/hdl/axi_gpio_v2_0_vh_rfs.vhd,incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"incdir="C:/AMDDesignTools/2025.2/Vivado/data/rsb/busdef"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"
prj_axi_axi_gpio_0_0.vhd,vhdl,xil_defaultlib,../../../bd/prj_axi/ip/prj_axi_axi_gpio_0_0/sim/prj_axi_axi_gpio_0_0.vhd,incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"incdir="C:/AMDDesignTools/2025.2/Vivado/data/rsb/busdef"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"
axi_bram_ctrl_v4_1_rfs.vhd,vhdl,axi_bram_ctrl_v4_1_13,../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/2f03/hdl/axi_bram_ctrl_v4_1_rfs.vhd,incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"incdir="C:/AMDDesignTools/2025.2/Vivado/data/rsb/busdef"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"
prj_axi_axi_bram_ctrl_0_0.vhd,vhdl,xil_defaultlib,../../../bd/prj_axi/ip/prj_axi_axi_bram_ctrl_0_0/sim/prj_axi_axi_bram_ctrl_0_0.vhd,incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"incdir="C:/AMDDesignTools/2025.2/Vivado/data/rsb/busdef"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"
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prj_axi_smartconnect_0_0.sv,systemverilog,xil_defaultlib,../../../bd/prj_axi/ip/prj_axi_smartconnect_0_0/sim/prj_axi_smartconnect_0_0.sv,incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"incdir="C:/AMDDesignTools/2025.2/Vivado/data/rsb/busdef"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"
dist_mem_gen_v8_0.v,verilog,dist_mem_gen_v8_0_17,../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ca90/simulation/dist_mem_gen_v8_0.v,incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"incdir="C:/AMDDesignTools/2025.2/Vivado/data/rsb/busdef"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"
axi_quad_spi_v3_2_rfs.vhd,vhdl,axi_quad_spi_v3_2_35,../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/9bdf/hdl/axi_quad_spi_v3_2_rfs.vhd,incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"incdir="C:/AMDDesignTools/2025.2/Vivado/data/rsb/busdef"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"
prj_axi_axi_quad_spi_0_1.vhd,vhdl,xil_defaultlib,../../../bd/prj_axi/ip/prj_axi_axi_quad_spi_0_1/sim/prj_axi_axi_quad_spi_0_1.vhd,incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"incdir="C:/AMDDesignTools/2025.2/Vivado/data/rsb/busdef"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"
prj_axi.v,verilog,xil_defaultlib,../../../bd/prj_axi/sim/prj_axi.v,incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"incdir="C:/AMDDesignTools/2025.2/Vivado/data/rsb/busdef"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/a415"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/00fe/hdl/verilog"incdir="../../../../axi_smpl.gen/sources_1/bd/prj_axi/ipshared/ec67/hdl"
glbl.v,Verilog,xil_defaultlib,glbl.v
