word_comm Project Status (10/04/2012 - 10:03:33)
Project File: word_comm.xise Parser Errors:
Module Name: word_comm Implementation State: Placed and Routed
Target Device: xc6slx150-3fgg676
  • Errors:
No Errors
Product Version:ISE 14.2
  • Warnings:
24 Warnings (24 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 51 184,304 1%  
    Number used as Flip Flops 51      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 59 92,152 1%  
    Number used as logic 59 92,152 1%  
        Number using O6 output only 17      
        Number using O5 output only 0      
        Number using O5 and O6 42      
        Number used as ROM 0      
    Number used as Memory 0 21,680 0%  
Number of occupied Slices 21 23,038 1%  
Nummber of MUXCYs used 40 46,076 1%  
Number of LUT Flip Flop pairs used 59      
    Number with an unused Flip Flop 11 59 18%  
    Number with an unused LUT 0 59 0%  
    Number of fully used LUT-FF pairs 48 59 81%  
    Number of unique control sets 6      
    Number of slice register sites lost
        to control set restrictions
21 184,304 1%  
Number of bonded IOBs 31 498 6%  
    Number of LOCed IOBs 31 31 100%  
    IOB Flip Flops 8      
Number of RAMB16BWERs 0 268 0%  
Number of RAMB8BWERs 0 536 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 1 16 6%  
    Number used as BUFGs 1      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 12 0%  
Number of ILOGIC2/ISERDES2s 8 586 1%  
    Number used as ILOGIC2s 8      
    Number used as ISERDES2s 0      
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 586 0%  
Number of OLOGIC2/OSERDES2s 0 586 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 384 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 180 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 4 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 6 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 4.43      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent木 10 4 09:57:56 2012024 Warnings (24 new)3 Infos (3 new)
Translation ReportCurrent木 10 4 10:02:45 2012000
Map ReportCurrent木 10 4 10:03:02 2012005 Infos (0 new)
Place and Route ReportCurrent木 10 4 10:03:21 2012000
Power Report     
Post-PAR Static Timing ReportCurrent木 10 4 10:03:31 2012003 Infos (0 new)
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 10/04/2012 - 10:03:33
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