Project Statistics |
PROPEXT_xilxMapPackRegInto_spartan6=For Inputs and Outputs |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2012-10-02T16:26:54 |
PROP_intWbtProjectID=1B11E7EF234E4C9399DA62B17740E9CC |
PROP_intWbtProjectIteration=3 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_xilxBitgCfg_Rate_spartan6=26 |
PROP_xilxBitgCfg_Unused=Float |
PROP_xilxBitgStart_IntDone=true |
PROP_xilxBitgSusWake_DriveAwakePin_spartan6=true |
PROP_xilxBitgSusWake_WakeupClk_spartan6=Internal Clock |
PROP_xilxNgdbld_AUL=true |
PROP_AutoTop=true |
PROP_DevFamily=Spartan6 |
PROP_xilxBitgCfg_GenOpt_BinaryFile=true |
PROP_DevDevice=xc6slx75 |
PROP_DevFamilyPMName=spartan6 |
PROP_DevPackage=fgg676 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-3 |
PROP_PreferredLanguage=Verilog |
FILE_UCF=3 |
FILE_VERILOG=4 |