AN1400 Project Status (10/06/2009 - 15:09:23) | |||
Project File: | AN1400.ise | Implementation State: | Programming File Generated |
Module Name: | word_comm |
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No Errors |
Target Device: | xc3s1400an-4fgg676 |
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36 Warnings |
Product Version: | ISE 11.3 |
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All Signals Completely Routed |
Design Goal: | Balanced |
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All Constraints Met |
Design Strategy: | Xilinx Default (unlocked) |
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0 (Setup: 0, Hold: 0) (Timing Report) |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 51 | 22,528 | 1% | ||
Number of 4 input LUTs | 62 | 22,528 | 1% | ||
Number of occupied Slices | 34 | 11,264 | 1% | ||
Number of Slices containing only related logic | 34 | 34 | 100% | ||
Number of Slices containing unrelated logic | 0 | 34 | 0% | ||
Total Number of 4 input LUTs | 62 | 22,528 | 1% | ||
Number of bonded IOBs | 34 | 502 | 6% | ||
IOB Flip Flops | 8 | ||||
Number of BUFGMUXs | 1 | 24 | 4% | ||
Average Fanout of Non-Clock Nets | 3.66 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | ‰Î 10 6 15:27:07 2009 | 0 | 25 Warnings | 0 | |
Translation Report | Current | ‰Î 10 6 15:35:04 2009 | 0 | 0 | 0 | |
Map Report | Current | ‰Î 10 6 15:35:09 2009 | 0 | 10 Warnings | 2 Infos | |
Place and Route Report | Current | ‰Î 10 6 15:35:25 2009 | 0 | 1 Warning | 4 Infos | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | ‰Î 10 6 15:35:28 2009 | 0 | 0 | 3 Infos | |
Bitgen Report | Current | ‰Î 10 6 15:35:37 2009 | 0 | 0 | 0 |
Secondary Reports | [-] | ||
Report Name | Status | Generated |