AN1400 Project Status (10/06/2009 - 15:09:23)
Project File: AN1400.ise Implementation State: Programming File Generated
Module Name: word_comm
  • Errors:
No Errors
Target Device: xc3s1400an-4fgg676
  • Warnings:
36 Warnings
Product Version:ISE 11.3
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
0 (Setup: 0, Hold: 0) (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 51 22,528 1%  
Number of 4 input LUTs 62 22,528 1%  
Number of occupied Slices 34 11,264 1%  
    Number of Slices containing only related logic 34 34 100%  
    Number of Slices containing unrelated logic 0 34 0%  
Total Number of 4 input LUTs 62 22,528 1%  
Number of bonded IOBs 34 502 6%  
    IOB Flip Flops 8      
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 3.66      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent‰Î 10 6 15:27:07 2009025 Warnings0
Translation ReportCurrent‰Î 10 6 15:35:04 2009000
Map ReportCurrent‰Î 10 6 15:35:09 2009010 Warnings2 Infos
Place and Route ReportCurrent‰Î 10 6 15:35:25 200901 Warning4 Infos
Power Report     
Post-PAR Static Timing ReportCurrent‰Î 10 6 15:35:28 2009003 Infos
Bitgen ReportCurrent‰Î 10 6 15:35:37 2009000
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 10/06/2009 - 15:40:51
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