QSYS_top | QSYS_top
1.0 |
2012.02.29.17:52:06 | Generation Report |
Output Directory | E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/ | ||||||||||||||||||||||||||||||||||||||||||||
Files | E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/QSYS_top.v (229303 bytes VERILOG)
E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/submodules/FIFOr.v (6925 bytes VERILOG) E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/submodules/FIFOw.v (6867 bytes VERILOG) E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/submodules/GPIF_Master.v (6779 bytes VERILOG) E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/submodules/GPIF_Mem.v (10207 bytes VERILOG) E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/submodules/GPIF_Reg.v (5719 bytes VERILOG) E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/submodules/QSYS_top_led.v (2192 bytes VERILOG) E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/submodules/QSYS_top_swin.v (1897 bytes VERILOG) E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/submodules/QSYS_top_notuse.v (2231 bytes VERILOG) E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/submodules/QSYS_top_onchip_memory2_0.hex (557069 bytes HEX) E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/submodules/QSYS_top_onchip_memory2_0.v (4122 bytes VERILOG) E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/submodules/AsyncSRAM.v (2151 bytes VERILOG) E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/submodules/altera_merlin_master_translator.sv (16802 bytes SYSTEM_VERILOG) E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/submodules/altera_merlin_slave_translator.sv (16043 bytes SYSTEM_VERILOG) E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/submodules/altera_merlin_master_agent.sv (8686 bytes SYSTEM_VERILOG) E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/submodules/altera_merlin_slave_agent.sv (19132 bytes SYSTEM_VERILOG) E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/submodules/altera_merlin_burst_uncompressor.sv (10373 bytes SYSTEM_VERILOG) E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/submodules/altera_avalon_sc_fifo.v (32228 bytes VERILOG) E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/submodules/QSYS_top_addr_router.sv (7462 bytes SYSTEM_VERILOG) E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/submodules/QSYS_top_id_router.sv (5955 bytes SYSTEM_VERILOG) E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/submodules/QSYS_top_id_router_004.sv (5967 bytes SYSTEM_VERILOG) E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/submodules/QSYS_top_id_router_005.sv (5966 bytes SYSTEM_VERILOG) E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/submodules/altera_merlin_burst_adapter.sv (37064 bytes SYSTEM_VERILOG) E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/submodules/altera_reset_controller.v (3595 bytes VERILOG) E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/submodules/altera_reset_synchronizer.v (3564 bytes VERILOG) E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/submodules/altera_reset_controller.sdc (1179 bytes SDC) E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/submodules/QSYS_top_cmd_xbar_demux.sv (6634 bytes SYSTEM_VERILOG) E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/submodules/QSYS_top_rsp_xbar_demux.sv (3474 bytes SYSTEM_VERILOG) E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/submodules/altera_merlin_arbitrator.sv (9460 bytes SYSTEM_VERILOG) E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/submodules/QSYS_top_rsp_xbar_mux.sv (14459 bytes SYSTEM_VERILOG) E:/Project/Design_data/qdesigns/CXCard4/RegEX/CX-Card4_GPIF_QSYS_Verilog/EP4CE55/QSYS_top/synthesis/submodules/altera_merlin_width_adapter.sv (35859 bytes SYSTEM_VERILOG) |
||||||||||||||||||||||||||||||||||||||||||||
Instantiations |
|