QSYS_top QSYS_top
1.0
2012.02.29.10:51:51 Generation Report
Output Directory D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/
Files D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/QSYS_top.v (229303 bytes VERILOG)

D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/FIFOr.v (6925 bytes VERILOG)
D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/FIFOw.v (6867 bytes VERILOG)
D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/GPIF_Master.v (6779 bytes VERILOG)
D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/GPIF_Mem.v (10207 bytes VERILOG)
D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/GPIF_Reg.v (5719 bytes VERILOG)
D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/QSYS_top_led.v (2192 bytes VERILOG)
D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/QSYS_top_swin.v (1897 bytes VERILOG)
D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/QSYS_top_notuse.v (2231 bytes VERILOG)
D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/QSYS_top_onchip_memory2_0.hex (557069 bytes HEX)
D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/QSYS_top_onchip_memory2_0.v (4122 bytes VERILOG)
D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/AsyncSRAM.v (2151 bytes VERILOG)
D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/altera_merlin_master_translator.sv (16802 bytes SYSTEM_VERILOG)
D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/altera_merlin_slave_translator.sv (16043 bytes SYSTEM_VERILOG)
D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/altera_merlin_slave_agent.sv (19132 bytes SYSTEM_VERILOG)
D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/altera_merlin_burst_uncompressor.sv (10373 bytes SYSTEM_VERILOG)
D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/altera_avalon_sc_fifo.v (32228 bytes VERILOG)
D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/altera_merlin_master_agent.sv (8686 bytes SYSTEM_VERILOG)
D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/QSYS_top_addr_router.sv (7462 bytes SYSTEM_VERILOG)
D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/QSYS_top_id_router.sv (5955 bytes SYSTEM_VERILOG)
D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/QSYS_top_id_router_004.sv (5967 bytes SYSTEM_VERILOG)
D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/QSYS_top_id_router_005.sv (5966 bytes SYSTEM_VERILOG)
D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/altera_merlin_burst_adapter.sv (37064 bytes SYSTEM_VERILOG)
D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/altera_reset_controller.v (3595 bytes VERILOG)
D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/altera_reset_synchronizer.v (3564 bytes VERILOG)
D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/altera_reset_controller.sdc (1179 bytes SDC)
D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/QSYS_top_cmd_xbar_demux.sv (6634 bytes SYSTEM_VERILOG)
D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/QSYS_top_rsp_xbar_demux.sv (3474 bytes SYSTEM_VERILOG)
D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/altera_merlin_arbitrator.sv (9460 bytes SYSTEM_VERILOG)
D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/QSYS_top_rsp_xbar_mux.sv (14459 bytes SYSTEM_VERILOG)
D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/altera_merlin_width_adapter.sv (35859 bytes SYSTEM_VERILOG)
Instantiations
QSYS_top
QSYS_top v1.0		 GPIF_Master as GPIF_Master_0
QSYS_top_led as led
QSYS_top_swin as swin
QSYS_top_notuse as notuse, pio_0
QSYS_top_onchip_memory2_0 as onchip_memory2_0
AsyncSRAM as sram
altera_merlin_master_translator as GPIF_Master_0_avalon_master_translator
altera_merlin_slave_translator as pio_0_s1_translator, swin_s1_translator, led_s1_translator, notuse_s1_translator, onchip_memory2_0_s1_translator, sram_avalon_slave_0_translator
altera_merlin_slave_agent as notuse_s1_translator_avalon_universal_slave_0_agent, swin_s1_translator_avalon_universal_slave_0_agent, led_s1_translator_avalon_universal_slave_0_agent, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent, sram_avalon_slave_0_translator_avalon_universal_slave_0_agent, pio_0_s1_translator_avalon_universal_slave_0_agent
altera_avalon_sc_fifo as notuse_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, swin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, sram_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo, pio_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo
altera_merlin_master_agent as GPIF_Master_0_avalon_master_translator_avalon_universal_master_0_agent
QSYS_top_addr_router as addr_router
QSYS_top_id_router as id_router, id_router_001, id_router_002, id_router_003
QSYS_top_id_router_004 as id_router_004
QSYS_top_id_router_005 as id_router_005
altera_merlin_burst_adapter as burst_adapter, burst_adapter_001
altera_reset_controller as rst_controller
QSYS_top_cmd_xbar_demux as cmd_xbar_demux
QSYS_top_rsp_xbar_demux as rsp_xbar_demux, rsp_xbar_demux_001, rsp_xbar_demux_002, rsp_xbar_demux_003, rsp_xbar_demux_004, rsp_xbar_demux_005
QSYS_top_rsp_xbar_mux as rsp_xbar_mux
altera_merlin_width_adapter as width_adapter, width_adapter_001, width_adapter_002, width_adapter_003
GPIF_Master
GPIF_Master v1.7
QSYS_top_led
altera_avalon_pio v11.1
QSYS_top_swin
altera_avalon_pio v11.1
QSYS_top_notuse
altera_avalon_pio v11.1
QSYS_top_onchip_memory2_0
altera_avalon_onchip_memory2 v11.1
AsyncSRAM
AsyncSRAM v1.1
altera_merlin_master_translator
altera_merlin_master_translator v11.1
altera_merlin_slave_translator
altera_merlin_slave_translator v11.1
altera_merlin_slave_agent
altera_merlin_slave_agent v11.1
altera_avalon_sc_fifo
altera_avalon_sc_fifo v11.1
altera_merlin_master_agent
altera_merlin_master_agent v11.1
QSYS_top_addr_router
altera_merlin_router v11.1
QSYS_top_id_router
altera_merlin_router v11.1
QSYS_top_id_router_004
altera_merlin_router v11.1
QSYS_top_id_router_005
altera_merlin_router v11.1
altera_merlin_burst_adapter
altera_merlin_burst_adapter v11.1
altera_reset_controller
altera_reset_controller v11.1
QSYS_top_cmd_xbar_demux
altera_merlin_demultiplexer v11.1
QSYS_top_rsp_xbar_demux
altera_merlin_demultiplexer v11.1
QSYS_top_rsp_xbar_mux
altera_merlin_multiplexer v11.1
altera_merlin_width_adapter
altera_merlin_width_adapter v11.1
Generation Messages
2012.02.29.10:51:18 [Debug] QSYS_top.GPIF_Master_0: Timing: QME:1/4.500s 2012.02.29.10:51:18 [Info] QSYS_top.swin: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. 2012.02.29.10:51:18 [Info] QSYS_top.onchip_memory2_0: User is required to provide memory initialization files for memory <onchip_memory2_0>. 2012.02.29.10:51:18 [Info] QSYS_top.onchip_memory2_0: Memory will be initialized from D:\PRIME\CX-Card4\pld\GPIF_QSYS_Verilog\Random1_64KB.hex 2012.02.29.10:51:18 [Info] QSYS_top.sram: Memory Size : 1024 KBytes 2012.02.29.10:51:18 [Debug] QSYS_top.sram: Timing: VAL:1/0.000s QME:1/0.780s 2012.02.29.10:51:18 [Info] QSYS_top: Generating QSYS_top "QSYS_top" for QUARTUS_SYNTH 2012.02.29.10:51:18 [Debug] QSYS_top: queue size: 0 starting:QSYS_top "QSYS_top" 2012.02.29.10:51:18 [Debug] Transform: PipelineBridgeSwap 2012.02.29.10:51:18 [Info] pipeline_bridge_swap_transform: After transform: 8 modules, 20 connections 2012.02.29.10:51:18 [Debug] Transform: ClockCrossingBridgeSwap 2012.02.29.10:51:18 [Debug] Transform: QsysBetaIPSwap 2012.02.29.10:51:18 [Debug] Transform: CustomInstructionTransform 2012.02.29.10:51:18 [Info] No custom instruction connections, skipping transform 2012.02.29.10:51:18 [Debug] Transform: TristateConduitUpgradeTransform 2012.02.29.10:51:18 [Debug] Transform: TranslatorTransform 2012.02.29.10:51:18 [Progress] min: 0 2012.02.29.10:51:18 [Progress] max: 1 2012.02.29.10:51:18 [Progress] current: 1 2012.02.29.10:51:18 [Progress] min: 0 2012.02.29.10:51:18 [Progress] max: 1 2012.02.29.10:51:18 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Info] merlin_translator_transform: After transform: 15 modules, 41 connections 2012.02.29.10:51:19 [Debug] Transform: DomainTransform 2012.02.29.10:51:19 [Debug] Transform merlin_domain_transform not run on matched interfaces GPIF_Master_0.avalon_master and GPIF_Master_0_avalon_master_translator.avalon_anti_master_0 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Debug] Transform merlin_domain_transform not run on matched interfaces pio_0_s1_translator.avalon_anti_slave_0 and pio_0.s1 2012.02.29.10:51:19 [Debug] Transform merlin_domain_transform not run on matched interfaces swin_s1_translator.avalon_anti_slave_0 and swin.s1 2012.02.29.10:51:19 [Debug] Transform merlin_domain_transform not run on matched interfaces led_s1_translator.avalon_anti_slave_0 and led.s1 2012.02.29.10:51:19 [Debug] Transform merlin_domain_transform not run on matched interfaces notuse_s1_translator.avalon_anti_slave_0 and notuse.s1 2012.02.29.10:51:19 [Debug] Transform merlin_domain_transform not run on matched interfaces onchip_memory2_0_s1_translator.avalon_anti_slave_0 and onchip_memory2_0.s1 2012.02.29.10:51:19 [Debug] Transform merlin_domain_transform not run on matched interfaces sram_avalon_slave_0_translator.avalon_anti_slave_0 and sram.avalon_slave_0 2012.02.29.10:51:19 [Info] merlin_domain_transform: After transform: 29 modules, 114 connections 2012.02.29.10:51:19 [Debug] Transform: RouterTransform 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Info] merlin_router_transform: After transform: 36 modules, 135 connections 2012.02.29.10:51:19 [Debug] Transform: TrafficLimiterTransform 2012.02.29.10:51:19 [Debug] Transform: BurstTransform 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Info] merlin_burst_transform: After transform: 38 modules, 141 connections 2012.02.29.10:51:19 [Debug] Transform: ResetAdaptation 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Info] reset_adaptation_transform: After transform: 39 modules, 143 connections 2012.02.29.10:51:19 [Debug] Transform: NetworkToSwitchTransform 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Info] merlin_network_to_switch_transform: After transform: 52 modules, 169 connections 2012.02.29.10:51:19 [Debug] Transform: WidthTransform 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Progress] min: 0 2012.02.29.10:51:19 [Progress] max: 1 2012.02.29.10:51:19 [Progress] current: 1 2012.02.29.10:51:19 [Info] merlin_width_transform: After transform: 56 modules, 181 connections 2012.02.29.10:51:19 [Debug] Transform: RouterTableTransform 2012.02.29.10:51:19 [Debug] Transform: ClockCrossingTransform 2012.02.29.10:51:19 [Debug] Transform: PipelineTransform 2012.02.29.10:51:19 [Debug] Transform: TrafficLimiterUpdateTransform 2012.02.29.10:51:19 [Debug] Transform: InterruptMapperTransform 2012.02.29.10:51:19 [Debug] Transform: InterruptSyncTransform 2012.02.29.10:51:19 [Debug] Transform: InterruptFanoutTransform 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses GPIF_Master "submodules/GPIF_Master" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_avalon_pio "submodules/QSYS_top_led" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_avalon_pio "submodules/QSYS_top_swin" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_avalon_pio "submodules/QSYS_top_notuse" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_avalon_pio "submodules/QSYS_top_notuse" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_avalon_onchip_memory2 "submodules/QSYS_top_onchip_memory2_0" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses AsyncSRAM "submodules/AsyncSRAM" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_router "submodules/QSYS_top_addr_router" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_router "submodules/QSYS_top_id_router" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_router "submodules/QSYS_top_id_router" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_router "submodules/QSYS_top_id_router" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_router "submodules/QSYS_top_id_router" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_router "submodules/QSYS_top_id_router_004" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_router "submodules/QSYS_top_id_router_005" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_reset_controller "submodules/altera_reset_controller" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_demultiplexer "submodules/QSYS_top_cmd_xbar_demux" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_demultiplexer "submodules/QSYS_top_rsp_xbar_demux" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_demultiplexer "submodules/QSYS_top_rsp_xbar_demux" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_demultiplexer "submodules/QSYS_top_rsp_xbar_demux" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_demultiplexer "submodules/QSYS_top_rsp_xbar_demux" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_demultiplexer "submodules/QSYS_top_rsp_xbar_demux" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_demultiplexer "submodules/QSYS_top_rsp_xbar_demux" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_multiplexer "submodules/QSYS_top_rsp_xbar_mux" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" 2012.02.29.10:51:19 [Debug] QSYS_top: "QSYS_top" reuses altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" 2012.02.29.10:51:20 [Debug] QSYS_top: queue size: 48 starting:GPIF_Master "submodules/GPIF_Master" 2012.02.29.10:40:23 [Debug] set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files 2012.02.29.10:40:23 [Debug] Command: C:/altera/11.1/quartus/bin/quartus_map.exe not_a_project --generate_hdl_interface=D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/GPIF_Master1_7/GPIF_Master.v --source=D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/GPIF_Master1_7/FIFOr.v --source=D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/GPIF_Master1_7/FIFOw.v --source=D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/GPIF_Master1_7/GPIF_Mem.v --source=D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/GPIF_Master1_7/GPIF_Reg.v --source=D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/GPIF_Master1_7/GPIF_Master.v --set=HDL_INTERFACE_OUTPUT_PATH=Z:/temp/alt5399_1524703807187753580.dir/0001_sopcqmap/ 2012.02.29.10:40:27 [Debug] Command took 4.490s 2012.02.29.10:51:20 [Debug] set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files 2012.02.29.10:51:20 [Debug] Command: C:/altera/11.1/quartus/bin/quartus_sh.exe -t Z:/temp/alt5399_1524703807187753580.dir/0003_sopcqmap/not_a_project_setup.tcl 2012.02.29.10:51:20 [Debug] Command: C:/altera/11.1/quartus/bin/quartus_map.exe not_a_project --generate_hdl_interface=D:\PRIME\CX-Card4\pld\GPIF_QSYS_Verilog\EP4CE40\GPIF_Master1_7\GPIF_Master.v --set=HDL_INTERFACE_OUTPUT_PATH=Z:/temp/alt5399_1524703807187753580.dir/0003_sopcqmap/ --set=HDL_INTERFACE_INSTANCE_NAME=inst --set=HDL_INTERFACE_INSTANCE_ENTITY=GPIF_Master "--set=HDL_INTERFACE_INSTANCE_PARAMETERS=REG_WRITE_WAIT=D\"0\";REG_READ_WAIT=D\"0\";REG_BASE_ADRS=B\"0000000000000000000000000000000000\";" 2012.02.29.10:51:20 [Debug] Command took 0.400s 2012.02.29.10:51:21 [Debug] Command took 0.610s 2012.02.29.10:51:21 [Info] GPIF_Master_0: "QSYS_top" instantiated GPIF_Master "GPIF_Master_0" 2012.02.29.10:51:21 [Debug] QSYS_top: queue size: 47 starting:altera_avalon_pio "submodules/QSYS_top_led" 2012.02.29.10:51:21 [Info] Starting classic module elaboration. 2012.02.29.10:51:23 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathZ:/temp/alt5399_1524703807187753580.dir/0004_sopclgen --no_splash --refresh Z:/temp/alt5399_1524703807187753580.dir/0004_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.02.29.10:51:25 [Info] Finished elaborating classic module. 2012.02.29.10:51:25 [Progress] Executing: C:/altera/11.1/quartus//sopc_builder/bin/sopc_builder --classic --generate Z:/temp/alt5399_1524703807187753580.dir/0004_sopclgen/yysystem.ptf 2012.02.29.10:51:25 [Info] Running sopc_builder... 2012.02.29.10:51:26 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathZ:/temp/alt5399_1524703807187753580.dir/0004_sopclgen --generate Z:/temp/alt5399_1524703807187753580.dir/0004_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.02.29.10:51:28 [Progress] No .sopc_builder configuration file(!) 2012.02.29.10:51:28 [Progress] . 2012.02.29.10:51:28 [Progress] # 2012.02.29 10:51:28 (*) Success: sopc_builder finished. 2012.02.29.10:51:29 [Info] led: "QSYS_top" instantiated altera_avalon_pio "led" 2012.02.29.10:51:29 [Debug] QSYS_top: queue size: 46 starting:altera_avalon_pio "submodules/QSYS_top_swin" 2012.02.29.10:51:29 [Info] Starting classic module elaboration. 2012.02.29.10:51:30 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathZ:/temp/alt5399_1524703807187753580.dir/0005_sopclgen --no_splash --refresh Z:/temp/alt5399_1524703807187753580.dir/0005_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.02.29.10:51:32 [Info] Finished elaborating classic module. 2012.02.29.10:51:32 [Progress] Executing: C:/altera/11.1/quartus//sopc_builder/bin/sopc_builder --classic --generate Z:/temp/alt5399_1524703807187753580.dir/0005_sopclgen/yysystem.ptf 2012.02.29.10:51:32 [Info] Running sopc_builder... 2012.02.29.10:51:33 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathZ:/temp/alt5399_1524703807187753580.dir/0005_sopclgen --generate Z:/temp/alt5399_1524703807187753580.dir/0005_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.02.29.10:51:35 [Progress] No .sopc_builder configuration file(!) 2012.02.29.10:51:35 [Progress] . 2012.02.29.10:51:35 [Progress] # 2012.02.29 10:51:35 (*) Success: sopc_builder finished. 2012.02.29.10:51:36 [Info] swin: "QSYS_top" instantiated altera_avalon_pio "swin" 2012.02.29.10:51:36 [Debug] QSYS_top: queue size: 45 starting:altera_avalon_pio "submodules/QSYS_top_notuse" 2012.02.29.10:51:36 [Info] Starting classic module elaboration. 2012.02.29.10:51:37 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathZ:/temp/alt5399_1524703807187753580.dir/0006_sopclgen --no_splash --refresh Z:/temp/alt5399_1524703807187753580.dir/0006_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.02.29.10:51:39 [Info] Finished elaborating classic module. 2012.02.29.10:51:39 [Progress] Executing: C:/altera/11.1/quartus//sopc_builder/bin/sopc_builder --classic --generate Z:/temp/alt5399_1524703807187753580.dir/0006_sopclgen/yysystem.ptf 2012.02.29.10:51:39 [Info] Running sopc_builder... 2012.02.29.10:51:40 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathZ:/temp/alt5399_1524703807187753580.dir/0006_sopclgen --generate Z:/temp/alt5399_1524703807187753580.dir/0006_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.02.29.10:51:41 [Progress] No .sopc_builder configuration file(!) 2012.02.29.10:51:42 [Progress] . 2012.02.29.10:51:42 [Progress] # 2012.02.29 10:51:42 (*) Success: sopc_builder finished. 2012.02.29.10:51:43 [Info] notuse: "QSYS_top" instantiated altera_avalon_pio "notuse" 2012.02.29.10:51:43 [Debug] QSYS_top: queue size: 43 starting:altera_avalon_onchip_memory2 "submodules/QSYS_top_onchip_memory2_0" 2012.02.29.10:51:43 [Info] Starting classic module elaboration. 2012.02.29.10:51:44 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathZ:/temp/alt5399_1524703807187753580.dir/0007_sopclgen --no_splash --refresh Z:/temp/alt5399_1524703807187753580.dir/0007_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.02.29.10:51:46 [Info] Finished elaborating classic module. 2012.02.29.10:51:46 [Progress] Executing: C:/altera/11.1/quartus//sopc_builder/bin/sopc_builder --classic --generate Z:/temp/alt5399_1524703807187753580.dir/0007_sopclgen/yysystem.ptf 2012.02.29.10:51:46 [Info] Running sopc_builder... 2012.02.29.10:51:47 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathZ:/temp/alt5399_1524703807187753580.dir/0007_sopclgen --generate Z:/temp/alt5399_1524703807187753580.dir/0007_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.02.29.10:51:49 [Progress] No .sopc_builder configuration file(!) 2012.02.29.10:51:49 [Progress] . 2012.02.29.10:51:50 [Progress] # 2012.02.29 10:51:50 (*) Success: sopc_builder finished. 2012.02.29.10:51:50 [Info] onchip_memory2_0: "QSYS_top" instantiated altera_avalon_onchip_memory2 "onchip_memory2_0" 2012.02.29.10:51:50 [Debug] QSYS_top: queue size: 42 starting:AsyncSRAM "submodules/AsyncSRAM" 2012.02.29.10:40:27 [Debug] set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files 2012.02.29.10:40:27 [Debug] Command: C:/altera/11.1/quartus/bin/quartus_map.exe not_a_project --generate_hdl_interface=D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/ASRAM1_1/AsyncSRAM.v --source=D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/ASRAM1_1/AsyncSRAM.v --set=HDL_INTERFACE_OUTPUT_PATH=Z:/temp/alt5399_1524703807187753580.dir/0002_sopcqmap/ 2012.02.29.10:40:28 [Debug] Command took 0.770s 2012.02.29.10:51:50 [Debug] set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files 2012.02.29.10:51:50 [Debug] Command: C:/altera/11.1/quartus/bin/quartus_map.exe not_a_project --generate_hdl_interface=D:\PRIME\CX-Card4\pld\GPIF_QSYS_Verilog\EP4CE40\ASRAM1_1\AsyncSRAM.v --source=D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/ASRAM1_1/AsyncSRAM.v --set=HDL_INTERFACE_OUTPUT_PATH=Z:/temp/alt5399_1524703807187753580.dir/0008_sopcqmap/ --set=HDL_INTERFACE_INSTANCE_NAME=inst --set=HDL_INTERFACE_INSTANCE_ENTITY=AsyncSRAM "--set=HDL_INTERFACE_INSTANCE_PARAMETERS=ADRS_WIDTH=D\"20\";" 2012.02.29.10:51:51 [Debug] Command took 0.750s 2012.02.29.10:51:51 [Info] sram: "QSYS_top" instantiated AsyncSRAM "sram" 2012.02.29.10:51:51 [Debug] QSYS_top: queue size: 41 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2012.02.29.10:51:51 [Info] GPIF_Master_0_avalon_master_translator: "QSYS_top" instantiated altera_merlin_master_translator "GPIF_Master_0_avalon_master_translator" 2012.02.29.10:51:51 [Debug] QSYS_top: queue size: 40 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.02.29.10:51:51 [Info] pio_0_s1_translator: "QSYS_top" instantiated altera_merlin_slave_translator "pio_0_s1_translator" 2012.02.29.10:51:51 [Debug] QSYS_top: queue size: 34 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.02.29.10:51:51 [Info] notuse_s1_translator_avalon_universal_slave_0_agent: "QSYS_top" instantiated altera_merlin_slave_agent "notuse_s1_translator_avalon_universal_slave_0_agent" 2012.02.29.10:51:51 [Debug] QSYS_top: queue size: 33 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.02.29.10:51:51 [Info] notuse_s1_translator_avalon_universal_slave_0_agent_rsp_fifo: "QSYS_top" instantiated altera_avalon_sc_fifo "notuse_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" 2012.02.29.10:51:51 [Debug] QSYS_top: queue size: 22 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2012.02.29.10:51:51 [Info] GPIF_Master_0_avalon_master_translator_avalon_universal_master_0_agent: "QSYS_top" instantiated altera_merlin_master_agent "GPIF_Master_0_avalon_master_translator_avalon_universal_master_0_agent" 2012.02.29.10:51:51 [Debug] QSYS_top: queue size: 21 starting:altera_merlin_router "submodules/QSYS_top_addr_router" 2012.02.29.10:51:51 [Info] addr_router: "QSYS_top" instantiated altera_merlin_router "addr_router" 2012.02.29.10:51:51 [Debug] QSYS_top: queue size: 20 starting:altera_merlin_router "submodules/QSYS_top_id_router" 2012.02.29.10:51:51 [Info] id_router: "QSYS_top" instantiated altera_merlin_router "id_router" 2012.02.29.10:51:51 [Debug] QSYS_top: queue size: 16 starting:altera_merlin_router "submodules/QSYS_top_id_router_004" 2012.02.29.10:51:51 [Info] id_router_004: "QSYS_top" instantiated altera_merlin_router "id_router_004" 2012.02.29.10:51:51 [Debug] QSYS_top: queue size: 15 starting:altera_merlin_router "submodules/QSYS_top_id_router_005" 2012.02.29.10:51:51 [Info] id_router_005: "QSYS_top" instantiated altera_merlin_router "id_router_005" 2012.02.29.10:51:51 [Debug] QSYS_top: queue size: 14 starting:altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter" 2012.02.29.10:51:51 [Info] burst_adapter: "QSYS_top" instantiated altera_merlin_burst_adapter "burst_adapter" 2012.02.29.10:51:51 [Debug] QSYS_top: queue size: 12 starting:altera_reset_controller "submodules/altera_reset_controller" 2012.02.29.10:51:51 [Info] rst_controller: "QSYS_top" instantiated altera_reset_controller "rst_controller" 2012.02.29.10:51:51 [Debug] QSYS_top: queue size: 11 starting:altera_merlin_demultiplexer "submodules/QSYS_top_cmd_xbar_demux" 2012.02.29.10:51:51 [Info] cmd_xbar_demux: "QSYS_top" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" 2012.02.29.10:51:51 [Debug] QSYS_top: queue size: 10 starting:altera_merlin_demultiplexer "submodules/QSYS_top_rsp_xbar_demux" 2012.02.29.10:51:51 [Info] rsp_xbar_demux: "QSYS_top" instantiated altera_merlin_demultiplexer "rsp_xbar_demux" 2012.02.29.10:51:51 [Debug] QSYS_top: queue size: 4 starting:altera_merlin_multiplexer "submodules/QSYS_top_rsp_xbar_mux" 2012.02.29.10:51:51 [Info] rsp_xbar_mux: "QSYS_top" instantiated altera_merlin_multiplexer "rsp_xbar_mux" 2012.02.29.10:51:51 [Debug] QSYS_top: queue size: 3 starting:altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" 2012.02.29.10:51:51 [Info] width_adapter: "QSYS_top" instantiated altera_merlin_width_adapter "width_adapter" 2012.02.29.10:51:51 [Info] Reusing file D:/PRIME/CX-Card4/pld/GPIF_QSYS_Verilog/EP4CE40/QSYS_top/synthesis/submodules/altera_merlin_burst_uncompressor.sv 2012.02.29.10:51:51 [Info] QSYS_top: Done QSYS_top" with 22 modules, 67 files, 1681470 bytes